Chapter 6: Output Compare Module

* Introduction
* 6.1 Single compare match mode
* 6.1.1 Single compare match, pin OCx driven high
* 6.1.2 Single compare match, pin OCx driven low
* 6.1.3 Single compare match, pin OCx toggles

* 6.5 Operation of the output compare module in SLEEP or IDLE mode
* 6.5.1 Operation of the output compare module in SLEEP mode
* 6.5.2 Operation of the output compare module in IDLE mode

Introduction

The output compare module has the task of comparing the value of the time base counter with the value of one or two compare registers depending on the Operation mode selected. It is able to generate a single output pulse or a sequence of output pulses when the compared values match; also, it has the ability to generate interrupts on compare match events.

The dsPIC30F4013 controller has 4 output compare modules whereas controller dsPIC6013 has 8. Each output compare channel can select which of the time base counters, TMR2 or TMR3, will be compared with the compare registers. The counter is selected by using control bit OCTSEL (OCxCON<3>).

The output compare module has several modes of operation selectable by using control bits OCM<2:0> (ocXcon<2:0>):

* Single compare match mode,
* Dual compare match mode generating either one output pulse or a sequence of output pulses,
* Pulse Width Modulation (PWM) mode.

NOTE: It is advisable, before switching to a new mode, to turn off the output compare module by clearing control bit OCM<2:0>.

Fig. 6-1 Functional diagram of output compare module
6.1 Single compare match mode

When control bits OCM<2:0> are set to 001, 010, or 011, the ouput compare module is set to the Single compare match mode. Now, the value loaded in the compare register OCxR is compared with time base counter TMR2 or TMR3. On a compare match event, depending on the value of OCM<2:0>, at the OCx output pin one of the following situations is possible:

* OCx pin is high, initial state is low, and interrupt is generated,
* OCx pin is low, initial state is high, and interrupt is generated,
* State of OCx pin toggles and interrupt is generated.

6.1.1 Single compare match, pin OCx driven high

In order to configure the output compare module for this mode, control bits OCM<2:0> are set to 001. Also, the time base counter (TMR2 or TMR3) should be selected. Initially, output pin OCx is set low and will stay low until a match event occurs between the TMRy and OCxR registers. One instruction clock after the compare match event, OCx pin is driven high and will remain high until a change of the mode or the module is disabled. TMRy goes on counting. Twop instruction clocks after OCx pin is driven high, the interrupt, OCxIF flag, is generated. Timing diagram of the single compare mode, set OCx high on compare match event is shown in Fig. 6-2.

Fig. 6-2 Timing diagram of the single compare mode, set OCx high on compare match event
6.1.2 Single compare match, pin OCx driven low

In order to configure the output compare module for this mode, control bits OCM<2:0> are set to 010. Also, the time base counter (TMR2 or TMR3) should be enabled. Initially, output pin OCx is set high and it stays high until a match event occurs between the TMRy and OCxR registers. One instruction clock after the compare match event OCx pin is driven low and will remain low until a change of the mode or the module is disabled. TMRy goes on counting. Two instruction clocks after OCx pin is driven low, the interrupt flag, OCxIF, is generated. Timing diagram of the single compare mode, set OCx low on compare match event is shown in Fig. 6-3.

Fig. 6-3 Timing diagram of the single compare mode,set OCx low on compare match event
6.1.3 Single compare match, pin OCx toggles

In order to configure the output compare module for this mode, control bits OCM<2:0> areset to 011. Also, the time base counter (TMR2 or TMR3) should be enabled. Initially, output pin OCx is set low and then toggles on each subsequent match event between the TMRy and OCxR registers. OCX pin is toggled one instruction clock the compare match event. TMRy goes on counting. Two instruction clocksafter the OCX pin is togglrd, the interrupt flag, OCxF, is generated. Figs. 6-4 and 6-5 show the timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy (PR2 or PR3)>OCxR (Fig. 6-4) or timer register PRy (PR2 or PR3)=OCxR (Fig. 6-5).

Fig. 6-4 Timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy>OCxR

Fig. 6-5 Timing diagrams of the single compare mode, toggle output on compare match event when timer register PRy =OCxR

NOTE: OCx pin is set low on a device RESET. In the single compare mode, toggle output on compare match event the operational OCx pin state can be set by the user software.
Example:

Output compare module 1 is in the single compare mode: toggle current output of pin OC1. The output compare module compares the values of OC1R and TMR2 registers; on equality, the output of OC1 pin is toggled

program Output_Compare_test1;

Procedure Output1 compare Int; org $18 //OC1 address in the interrupt vector table

begin

TRISD = 0;             //OC1 (RD0) is output pin

IPC0     = IPC0 or $0100; //Priority level of interrupt OC1IP<2:0>=1

IEC0     = IEC0 or $0004; //Output compare 1 enable interrupt

OC1R     = 10000; //OCR=TMR2 instant of level change at OC1

PR2     = $FFFF; //PR2 value maximal, time base 2 free-running

T2CON = $8030; //Time base 2 operates using prescaler 1:256 and internal clock

OC1CON = $0003; //Output compare 1 module configuration,TMR2 selected

           //Single compare mode, pin OC1 toggles

while TRUE do      //Endless loop

    nop;

end.

In the interrupt routine the request for the flag Output compare interrupt module is reset. At setting time base 2, preset register PR2 is set to the maximum value in orde to enable the free-running mode over the whole range, 0-65335. The value of OC1R defines the time of the change of state of pin OC1, i.e. of the duty cycle. The output compare module is configured to change the state of pin OC1 on single compare match with the value of OC1R.
6.2 Dual compare match mode

When control bits OCM<2:0> are set to 100 or 101, the output compare module is cobfigured for the dual compare match mode. In this mode the module uses two registers, OCxR and OCxRS, for the compare match events.

The values of both registers are compared with the time base counter TMR2 or TMR3. On a compare match event of the OCxR register and register TMR2 or TMR3 (selectable by control bit OCTSEL), the leading edge of the pulse is generated at the OCx pin; the register OCxRS is then compared with the same time base register and on a compare match evenet, the trailing edge at the OCx pin is generated.

Depending on the value of control bit OCM<2:0> at the output pin OCx is generated:

* single pulse and an interrupt request,
* a sequence of pulses and an interrupt request.

6.2.1 Dual compare match mode, single output pulse at pin OCx

When control bits OCM<2:0> are set to 100, the output compare module is configured for the dual compare match (OCxR and OCxRS registers), single output pulse mode. By setting the control bits OCTSEL the time base counter for comparison is selected. v. Two instruction clocks after pin OCx is driven low, an interrupt request OCxIF for the output compare module is generated. Pin OCx will remain low until a mode change has been made or the module is disabled. If the contents of time base register PRy< OCxRS < PRy).

Fig. 6-6 Timing diagram of the operation of the output compare module in the dual compare match mode, single pulse at the output pin OCx
6.2.2 Dual compare match mode, sequence of output pulses at pin OCx

When control bits OCM<2:0> are set to 101 the output compare module is configured for the dual compare match (OCxR and OCxRS registers), a sequence of output pulses is generated at the output OCx pin. After a compare match occurs between the compare time base (TMR2 or TMR3) and OCxR registers, the output pin OCx is driven high, i.e. the leading edge is generated at pin OCx. When a compare match occurs between the time base (TMR2 or TMR3) and OCxRS registers, the trailing edge at pin OCx is generated, i.e. pin OCx is driven low. Two instruction clocks after, an interrupt request for the otput compare module is generated. In this mode it is not necessary to reset the ouput compare module in order that the module could react on equalization of the TRy and OCxR or OCxRS registers. Even if the interrupt of the output compare module is enabled (OCxIE is set), it is required that in the interrupt routine the interrupt request flag of the output compare module OCxIF is reset.

If the preset register PRy < OCxRS, the trailing edge at pin OCx will not be generated. Fig. 6-7 shows an example of operation of the output compare module in the dual compare match mode, a sequence of output pulses at the output pin OCx (OCxR < OCxRS < PRy).

Fig. 6-7 Timing diagram of the operation in the dual compare match mode, pulse sequence at the output pin OCx
Example:

The output compare module compares the value of registers OC1R and OC1RS with the value of the counter TMR2 of the time base 2 and on compare match event toggles the logical level at pin OC1.

program Output_compare_test2;

procedure Output1CompareInt; org $18;//Address of OC1 in the interrupt table

begin

 IFS0    :=0;   //Reseting of interrupt OC1 module flag

end;

begin

  TRISD    := IPC0 or $0100; //OC1 (RD0) is output

  IPC0    := IEC0 or $0004; //Output  Compare module 1 interrupt enable

  OC1R    := 30000; //If OC1R=TMR2, leading edge at pin OC1

  OC1RS     := 100;   //If OC1RS=TMR2, trailing edge at OC1

  PR2    := $FFFF; //PR2 at maximum, time base 2 free-running

  T2CON    := $8030; //Time base 2 operates with prescaler 1:256 and internal clock

  OC1CON    := $0005  //Configuration of Output Compare 1 module, TMR2 selected, dual compare match, pulse sequence

while TRUE do      // Endless loop

    nop;

end.

In the interrupt routine the interrupt request flag of the Output Compare module is reset. In presetting timer 2, register PR2 is set to the maximum value in order to enable free-running mode of the timer within the entire range of values 0 to 65535. The value of OC1R defines the instant of the leading edge at pin OC1, the value of OC1RS defines the instant of the trailing edge. The Otput Compare module is configured to toggle continually the logical level at pin OC1 on dual compare match event with the values of registers OC1R and OC1RS.
6.3 The Pulse Width Modulation (PWM) Mode

When control bits OCM<2:0> are set to the values 110 or 111, the output compare module is configured for the pulse width modulation (PWM) mode. The PWM mode is available without fault protection input or with fault protection input. For the second PWM mode the OCxFA or OCxFB input pin is used. Fig. 6-8 shows an example of microcontroller dsPIC30F4013 connection to the inverter including the feedback error signal. The inverter controls the operation of motor M

Fig. 6-8 dsPIC30F4013 connection to the inverter including the feedback error signal
6.3.1 PWM mode without fault protection input

When control bits OCM<2:0> are set to 110, the output compare module operates in this mode. In PWM mode the OCxR register is a read only slave duty cycle register. The OCxRS is a buffer register written by the user to update the PWM duty cycle.On every timer to period register match event (end of PWM period), the duty cycle register, OCxR, is loaded with the contents of OCxRS.The interrupt flag is asserted at the end of each PWM period.

When configuring the output compare module for PWM mode of operation, the following steps should be taken:

1. Set the PWM period by writing to the selected timer period register, PRy.
2. Set the PWM duty cycle by writing to the OCxRS register.
3. Write the OCxR register with the initial duty cycle.
4. Enable interrupts for the selected timer.
5. Configure the output compare module for one of two PWM operation modes by writing 100 to control bits OCM<2:0> (OCxCON<2:0>).
6. Set the TMRy prescale value and enable the selected time base.

NOTE: The OCxR register should become a read only duty cycle register before the output compare module is first enabled (OCM<2:0>=000).
6.3.2 PWM mode with fault protection input pin

When the control bits OCM<2:0> areset to 111, the outpu compare module is configured for the PWMmode of operation. All functions derscribed in section 6.3.1 apply, with the addition that in this mode in addition to the output pin OCX the use is made of the signal from the input pin OCxFA for the output compare channels 1 to 4 or from the inpit pin OCxFB for the output compare channels 5 to 8. The signal at input pin OCxFA or OCxFB is a feedback error signal of the inverter related to a possible hazardous state of operation of the inverter. If the input pin OCxFA or OCxFB is low, the inverter is onsidered to be in a hazardous (error) state. Then the output OCx pin of the output compare module operating in the PWM mode is disabled automatically and the pin is driven to the high impedance state. The user may elect to provide a pull-down or pull-up resistor in order to define the state of OCx pin which is in thisstate disconnected from the rest of the output compare module. In the state of inverter fault, upon detection of the fault condition and disabling of pin OCx, the respective interrupt flag is asserted and in the register OCxCON the OCFLT bit (OCxCON<4>) is set. If enabled, an interrupt of the output compare module will be generated.

NOTE: The external fault pins, OCxFA or OCxFB, while the output compare module operates in PWM mode with fault protection input pin, will continue to protect the module while it is in SLEEP or IDLE mode.
6.4 PWM period and duty cycle calulation
6.4.1 PWM period

The PWM period, specified by the value in the PRy register of the selected timer y, is calculated by:

TPWM=(PRy +1)TCY(TMRy prescale value),

and the PWM frequencyby:

fPWM=1/TPWM.
Example:

Calculation of the PWM period for a microcontroller having a 10MHz clock with x4 PLL, Device clock rate is 40MHz. The instruction clock frequency is FCY=FOSC/4, i.e. 10MHz. Timer 2 prescale setting is 4. Calculate the PWM period for the maximum value PR2=0xFFFF=65535.

TPWM = (65535+1) x 0.1µs x (4) = 26.21 ms, i.e. fPWM = 1/TPWM = 38.14 Hz.
6.4.2 PWM duty cycle

The PWM duty cycle is specified by the value written to the register OCxRS. It can be written to at any time within the PWM cycle, but the duty cycle value is latched into OCxR when the PWM period is completed. OCxR is a read only register. This provides a double buffering for the PWM duty cycle.

If the duty cycle register,OCxR, is loaded with 0000, the duty cycle is zero and pin OCx will remain low throughout the PWM period.

If the duty cycle register is greater that PRy, the output pin OCx will remain high throughout the PWM period (100% duty cycle).

If OCxR is equal to PRy, the OCx pin will be high in the first PWM cycle and low in the subsequent PWM cycle.

NOTE: In order to achieve as fine as possible control of PWM, it is necessary to enable as high as possible duty cycle adjustment. This is accomplished by adjusting the prescale value, clock value, and PWM frequency to achieve the highest possible value of PRy thus achieving the highest number of adjustment levels, i.e. the highest resolution.
6.4.3 Maximum resolution

The maximum resolution is calculated by the following formula:

Max PWM resolution [bits] = (log10TPWM - log(TCY x prescale value TMRy)) / log102
Example:

Calculation of the PWM period for a microcontroller having a 10MHz clock with x4 PLL, Device clock rate is 40MHz. The instruction clock frequency is FCY=FOSC/4, i.e. 10MHz. Timer 2 prescale setting is 4. Calculate the maximum resolution for PWM frequency 48Hz.

Max PWM resolution [bits] = (log10(1/48) – log10(0.1µs x 4)) / log102 = 15.66 bits.

For this value of the PWM period and other selected parameters (prescale value, clock) it turns out that the PWM mode operates with almost maximum resolution.

Fig. 6-9 Timing diagram of the PWM mode of the output compare module
6.5 Operation of the output compare module in SLEEP or IDLE mode
6.5.1 Operation of the output compare module in SLEEP mode

When the device enters SLEEP mode, the system clock is disabled. During SLEEP, the state of the output pin OCx is held at the same level as prior to entering SLEEP. For example, if the output pin OCx was high and the CPU entered the SLEEP state, the pin will stay high until the the microcontroller wakes up.
6.5.2 Operation of the output compare module in SLEEP mode

When the device enters IDLE mode, the OCSIDL control bit (OCxCON<13>) selects if the output compare module will stop or continue operation in IDLE mode.

If OCSIDL = 0, the module will continue operation only if if the selected time base is set to operate in IDLE mode (TSIDL = 0).

If OCSIDL = 1, the module will discontinue operation in IDLE mode as it does for SLEEP mode.

NOTE: The input pins OCxFA and OCxFB during SLEEP or IDLE modes, if enabled for use, will continue to control the associated output pin OCx, i.e. disconnect the output pin OCx if they are low.

Fig. 6-10a Pinout of microcontroller dsPIC30F4013, output compare module pins marked

Fig. 6-10b Pinout of microcontroller dsPIC30F6014, output compare module pins marked

Finally, a description is given of the output registers of the output compare module of microcontroller dsPIC30F4013.
name     ADR     15     14     13     12-5     4     3     2     1     0     Reset State
OC1RS     0×0180     Output Compare 1 Secondary Register     0×0000
OC1R     0×0182     Output Compare 1 Main Register     0×0000
OC1CON     0×0184     -     -     OCSIDL     -     OCFLT     OCTSEL     OCM<2:0>     0×0000
OC2RS     0×0186     Output Compare 2 Secondary Register     0×0000
OC2R     0×0188     Output Compare 2 Main Register     0×0000
OC2CON     0×018A     -     -     OCSIDL     -     OCFLT     OCTSEL     OCM<2:0>     0×0000
OC3RS     0×018C     Output Compare 3 Secondary Register     0×0000
OC2R     0×018E     Output Compare 3 Main Register     0×0000
OC3CON     0×0190     -     -     OCSIDL     -     OCFLT     OCTSEL     OCM<2:0>     0×0000
OC4RS     0×0192     Output Compare 4 Secondary Register     0×0000
OC4R     0×0194     Output Compare 4 Main Register     0×0000
OC4CON     0×0196     -     -     OCSIDL     -     OCFLT     OCTSEL     OCM<2:0>     0×0000

Table 6-1 Register map associated with output compare module

OCSIDL – output compare stop bit in IDLE state (OCSIDL=0 the module is active in
IDLE state, OCSIDL=1 the module in inactive in IDLE state)
OCFLT – PWM FAULT state bit (OCFLT=0 no FAULT occured, OCFLT=1 FAULT
occured, hardware reset only)
OCTSEL – Output Compare timer select bit (OCTSEL=0 TMR2 selected, OCTSEL=1
TMR3 selected)
OCM <2:0> - mode select bit of the Output Compare Module
000 – Output Compare Module disabled
001 - Single compare match mode, pin OCx driven high
010 - Single compare match mode, pin OCx driven low
011 -  Single compare match mode, pin OCx toggles
100 - Dual compare match mode, single output pulse at pin OCx
101 - Dual compare match mode, sequence of output pulses at pin OCx
110 - PWM mode without fault protection input
111 - PWM mode with fault protection input

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